In the rapidly advancing field of semiconductor device manufacturing, high-k gate dielectric materials, i.e. gate dielectric materials having a dielectric constant, k, of greater than about 3.9, are favored because they produce a smaller equivalent oxide thickness (EOT) and therefore faster transistor devices. There have been many different approaches for incorporating various high-k gate dielectric materials into semiconductor device manufacturing, each with associated shortcomings. The high-k gate dielectric material must be chosen and formed for compatibility with the processing requirements of the other materials used to form the transistor gates. Another complication is that NMOS and PMOS gate structures operate under different conditions and each benefits from being formed of associated materials particularly suited to the device requirement of the respective NMOS or PMOS transistor. Each advantageously operates at a low threshold voltage, Vt. As such, it is increasingly difficult to tailor distinct high-k gate dielectrics for NMOS and PMOS devices formed on the same semiconductor substrate and to integrate each into one manufacturing process that also provides and utilizes other materials needed to form the respective gate structures for PMOS and NMOS transistors. The push to produce NMOS and PMOS transistors that each include a high-k gate dielectric and are formed with different materials to each have suitably low Vt's, is indeed a challenge.
One attempt to produce a semiconductor device having NMOS and PMOS transistors formed of high-k gate dielectric materials is described in U.S. Pat. No. 5,763,922 to Chau which provides an NMOS gate dielectric being nitrogen-rich at the gate dielectric-substrate interface whereas the PMOS gate dielectric is less nitrogen-rich at the gate dielectric-substrate interface. U.S. Pat. No. 6,893,924 to Visokay provides PMOS and NMOS transistors formed using different combinations of low work function metal nitride layers and high work function metal nitride layers. U.S. Pat. No. 7,229,893 to Wang et al. teaches the introduction of various dopant materials into the gate dielectric to form an amorphous portion thereof. One shortcoming associated with U.S. Pat. No. 7,229,893 is that the introduction of the dopant impurities into the high-k gate dielectric, renders the gate dielectric material difficult to remove by etching.
It would be desirable to form both NMOS and PMOS transistors on the same semiconductor substrate using an economy of process operations to produce NMOS and PMOS metal gate/high-k dielectric transistors, each with a suitably low threshold voltage.